Recently, downsizing of semiconductor devices used for portable electronic devices such as a portable phone, and a nonvolatile recording medium of an IC memory card have been in high demand. Fulfilling this demand requires techniques for efficiently packaging the semiconductor chip. The package-on-package process for layering the packages on which the semiconductor chip is mounted has been developed as an example of one of these techniques.
Each of FIGS. 1A, 1B, 2A and 2B is a sectional view showing the semiconductor device and the package-on-package structure as a generally employed example. FIGS. 1A and 1B, for example, show an exemplary case where a semiconductor chip is mounted on a wiring substrate with a face-up structure through a wire bonding. Meanwhile, FIGS. 2A and 2B show an exemplary case where the semiconductor chip is mounted on the wiring substrate with a face-down structure through a stud bump. Referring to FIG. 1A, a semiconductor chip 12 is mounted on a wiring substrate 10 with a die adhesive material 14. The semiconductor chip 12 and the wiring substrate 10 are electrically coupled via a wire 23. The semiconductor chip 12 is sealed with a sealing resin 16. A land electrode 22 is positioned on the wiring substrate 10 on the side of the semiconductor chip 12. A solder ball 18 is positioned on the wiring substrate 10 on the side away from the semiconductor chip 12 via a land electrode 20. The land electrode 22 and the solder ball 18 are electrically coupled. FIG. 1B is a view showing a semiconductor structure having the semiconductor devices shown in FIG. 1A layered. Referring to FIG. 1B, the solder ball 18 of an upper semiconductor device 24 is connected to the land electrode 22 of a lower semiconductor device 26. In this way, the upper semiconductor device 24 is electrically coupled with the lower semiconductor device 26.
Referring to FIG. 2A, the semiconductor chip 12 is mounted on the wiring substrate 10 using stud bumps 28. An underfill material 30 is filled between the semiconductor chip 12 and the wiring substrate 10. The other structure is the same as the one shown in FIG. 1A. FIG. 2B is a view showing a semiconductor structure formed by layering the semiconductor devices shown in FIG. 2A. The method of layering those semiconductor devices is the same as the case shown in FIG. 1B, and the explanation thereof, thus, will be omitted.
Japanese Patent Application Publication No. JP-A-2000-200800 discloses a technology for forming a via post with a stud bump in a semiconductor wafer electrode, which is used for connecting a semiconductor chip and a solder ball that serves as a packaged terminal in a chip-size-package.
In the generally employed example 1, the solder ball 18 is used as the electrode when the semiconductor devices are layered, and also as the electrode when the semiconductor device is mounted on the motherboard, for example. The semiconductor device may be downsized by reducing electrode pitch of the solder ball 18. However, the solder ball 18 is spherically or elliptically shaped, and as such requires enough spacing from the adjacent electrode so as to not cause short-circuiting when the solder ball is melted. Over-reduction of the electrode pitch of the solder ball may occur, to the extent that a high-precision mount technique is required to mount the solder ball to the motherboard, and accordingly, high-precision inspection jigs are required in the electric inspection step. Therefore, the electrode pitch of the solder ball is required to be wide, which may hinder the downsizing of the semiconductor device.